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1 publication order number : le2464c/d www.onsemi.com ? semiconductor component s industries, llc, 2015 february 2015 - rev. 2 ordering information see detailed ordering and shipping info rmation on page 16 of this data sheet. le2464c overview the le2464c (hereinafter referred to as ?this device?) is two-wire serial interface eeprom (electrically erasab le and programmable rom). this device realizes high speed and a high level reliability by high performance cmos eeprom technology. this device is compatible with i 2 c memory protocol, therefore it is best suited for application that requires re-writable nonvolatile parameter memory. function ?? capacity : 64k bits (8k ? 8 bits) ? single supply voltage : 1.7v to 3.6v ? operating temperature : ? 40oc to +85oc ? interface : two wire serial interface (i 2 c bus*) ?? operating clock frequency : 400khz ? low power consumption ? : standby : 2 a (max.) : active (read) : 0.5 ma (max.) ? automatic page write mode : 32 bytes ? read mode : sequential read and random read ? slave address : slave addr ess in 7 bit format is 0 ? 50 or 0 ? 54 depending of polarity of pin b3 (test) ? erase/write cycles : 10 6 cycles (page write) ? data retention : 20 years ? high reliability : adopts proprietary symmetric memory array configuration (usp6947325) hardware write protect feature noise filters connected to scl and sda pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : wlp6(1.20 ? 0.80) 0.33mm height specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit supply voltage ? 0.5 to +4.6 v dc input voltage ? 0.5 to v cc +0.5 v over-shoot voltage ? 1.0 to v cc +1.0 v storage temperature tstg ? 65 to +150 ? c cmos lsi 64-kb i 2 c cmos serial eeprom * this product is licensed from silicon storage technology, inc. (usa). * i 2 c bus is a trademark of philips corporation. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. wlcsp6, 0.80x1.20
le2464c www.onsemi.com 2 recommended operating conditions parameter symbol conditions ratings unit min typ max operating supply voltage 1.7 3.6 v operating temperature ? 40 +85 ? c dc electrical characteristics parameter symbol conditions ratings unit min typ max supply current at reading i cc 1 f = 400khz, v cc = v cc max 0.5 ma supply current at writing i cc 2 f = 400khz, twc = 5ms, v cc = v cc max 3ma standby current i sb v in = v cc or gnd 2 a input leakage current i li v in = gnd to v cc , v cc = v cc max ? 2.0 +2.0 a output leakage current i lo v in = gnd to v cc , v cc = v cc max ? 2.0 +2.0 a input low voltage v il v cc ? 0.3 v input high voltage v ih v cc ? 0.7 v output low voltage v ol i ol = 0.7ma, v cc = 1.7v 0.2 v i ol = 1.0ma, v cc = 1.7v 0.4 v i ol = 2.0ma, v cc = 2.5v 0.4 v capacitance at ta = 25 ? c, f = 1mhz parameter symbol conditions max unit in/output pin capacitance c i/o v i/o = 0v (sda) 10 pf input pin capacitance c i v in = 0v 10 pf ac electric characteristics input pulse level 0.1v cc to 0.9v cc input pulse rise / fall time 20ns output detection voltage 0.5v cc output load 50pf + pull up resistor 3.0k ? r=3.0k ? sda v cc c=50pf output load circuit functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
le2464c www.onsemi.com 3 fast mode parameter symbol ratings unit min typ max slave mode scl clock frequency f scls 0 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl sda rise time t r 300 ns scl sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write time t wc 5ms standard mode parameter symbol ratings unit min typ max slave mode scl clock frequency f scls 0 100 khz scl clock low time t low 4700 ns scl clock high time t high 4000 ns sda output delay time t aa 100 3500 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 4700 ns start condition hold time t hd.sta 4000 ns data in setup time t su.dat 250 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 4000 ns scl sda rise time t r 1000 ns scl sda fall time t f 300 ns bus release time t buf 4700 ns noise suppression time t sp 100 ns write time t wc 5ms
le2464c www.onsemi.com 4 package dimensions unit : mm wlp6(1.2 ? 0.8) 0.33mm height 0.80.05 1.20.05 top view side view bottom view side view b a b 0.2 0.4 0.4 0.2 2 1 3 a b s 0.05 m ab 6 x 0.200.05 0.33 max 0.080.05 s s 0.08 wlcsp6, 0.80x1.20 case 567hm issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max --- millimeters a1 d 0.80 bsc e b 0.15 0.25 e 0.40 bsc 0.33 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.08 c 6x b 12 b a 0.05 c a a1 c 0.03 0.13 1.20 bsc pitch 0.20 6x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.05 c 2x top view side view bottom view note 3 recommended a1 package outline e pitch 3
le2464c www.onsemi.com 5 pin assignment pin descriptions a1 scl serial clock input a2 wp write protect a3 vcc power supply b1 sda serial data in/output b2 gnd ground b3 test slave device address 2 block diagram eeprom array x decoder hi g h volta g e g enerator serial-parallel converter address generator y decoder & sense amp condition detector i/o buffer input buffer serial controller scl sda write controller te s t wp ball side view a 1 2 b 3 test gnd sda vcc scl wp b 1 2 3 a scl wp vcc sd a test top view gnd
le2464c www.onsemi.com 6 bus timing write timing pin function scl (serial clock) the scl signal is used to control serial input data timi ng. the scl is used to latch input data synchronously at the rising edge and read output dat a synchronously at the falling edge. sda (serial input / output data) the sda pin is bidirectional for serial data transfer. it is an open-drain structure t hat needs to be pulled up by resistor. test (slave address) test pin represents s2. test pulled high (1.8v) results in 7bit device address of 0x54. test pulled low results in 7 bit device address of 0x50. the test must be tied to v cc or gnd. wp (write protect) when the wp input is high, write protection is enabl ed. when wp input is eit her low or floating, write protection is disabled. the read operation is always activated irrespective of the wp pin status. t buf t su.sto t r scl sda/in sda/out t su.sta t hd.dat t high t low t su.dat t dh t aa t f t hd.sta t sp t sp write data acknowledge stop condition start condition t wc scl sda d0
le2464c www.onsemi.com 7 functional description the device supports the i 2 c protocol. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to a receiver. the devic e that controls the data transfer is known as the bus master, and the other as the slave device. 1) start condition a start condition needs to start the eeprom operation, it is to set falling edge of the sda while the scl is stable in the high status. 2) stop condition a start condition is identified by rising edge of the sd a signal while the scl is stable in the high status. the device becomes the standby mode from a read oper ation by a stop condition. in a write sequence, a stop condition is trigger to terminate the write data input s and it is trigger to start the internal write cycle. after the internally write cycle time which is sp ecified as twc, the devic e enters a standby mode. 3) data input during data input, the device latches the sda on the ri sing edge of the scl. for correct the operation, the sda must be stable during the rising edge of the scl. stop condition start condition scl sda t su.sta t hd.sta t su.sto scl sda t su.dat t hd.dat
le2464c www.onsemi.com 8 4) acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte data transfer. the receiver sends a zero to acknowledge that it has received each word (device code, slave address etc) from the transmitter. 5) device addressing to transmit between the bus master and slave device (eeprom ), the master must send a start condition to the eeprom. the device address word of the eeprom consists of 4-bit device code, 3-bit slave device address code and 1-bit read/write code. by sending these, it becomes possible to communicate between the bus master and the eeprom. the upper 4-bit of the devic e address word are called the device code, the device code of the eeprom uses 1010b fixed code. this device has the 3-bit of the slave device address as the slave address (s0, s1, s2). the value of s0 and s1 fixed s0=0, s1=0 internally. this device can connect up to two devices on the bus controlled by s2 value. when the device code is received on the sda, the device only responds if slave address pin tied to vcc or gnd is the same as the slave address signal input. the 8 th bit is the read/write bit. the bit is set to 1 for read operation and 0 for write operation. if a matc h occurs on the device code, the corresponding device gives an acknowledgement on sda during the 9 th bit time. if device does not match the device code, it deselects itself from the bus, and goes into the standby mode. use the random read command when you execute reading after the slave device was switched. 1 0 1 0 s2 s1 s0 r/w device code slave address msb lsb device address word acknowledge bit output start condition 1 scl ( from transmitter ) sda (from transmitter) sda (eeprom output) 8 9 t aa t dh
le2464c www.onsemi.com 9 6) eeprom write operation 6)-1. byte write the write operation requires a 7-bit device address word with the 8 th bit = 0 (write). then the eeprom sends acknowledgement 0 at the 9 th clock cycle. after these, the eeprom receives word address (a15 to a8), and the eeprom outputs acknowledgement 0. and then, the eeprom receives word address (a7 to a0), and the eeprom outputs acknowledgement 0. then the eeprom receives 8-bit write data, the eeprom outputs acknowledgement 0 after receipt of write data. if the eeprom receives a stop condition, the eeprom enters an in ternally timed (twc) write cycle and terminates receipt of inputs until completion of the write cycle. 6)-2. page write the page write allows up to 32 bytes to be written in a single write cycle. the page write is the same sequence as the byte write except for inputting the mo re write data. the page write is initiated by a start condition, device code, device address, memo ry address(n) and write data(n) with every 9 th bit acknowledgement. the device enters the page write operation if this device receives more write data(n+1) instead of receiving a stop condition. the page address (a0 to a4) bits are automatically incremented on receiving write data(n+ 1). the device can continue to rece ive write data up to 32 bytes. if the page address bits reaches the last address of the page, the page addres s bits will roll over to the first address of the same page and previous write data will be overwritten. after these, if the device receives a stop condition, the device enters an internally timed (twc(n+x)) write cycle and terminates receipt of inputs until completion of the write cycle. s d a word address 0 1 0 s1 1 w start a c k a c k a c k sto p a 11 a 10 a9 a8 d7 d6 d5 d4 d3d2d1d0 data r/w s2 a c k a7 a6 a5 a4 a3 a2 a1 a0 s0 a15 ~ a13: don?t care a 12 a 14 a 13 a 15 access from master device s d a 0 1 0 s1 1 w start ack ack ack data(n) r/w s2 ack s0 word address(n) a 11 a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3d2d1d0 a c k sto p d7 d6 ~ d1 d0 a c k a c k data(n+x) a15 ~ a13: don?t care data(n+1) a c k a c k d7d6 ~ d1d0 d7d6 ~ d1d0 d7 d6 ~ d1 d0 a 12 a 14 a 13 a 15 access from master device
le2464c www.onsemi.com 10 6)-3. acknowledge polling the acknowledge polling operation is used to show if t he eeprom is in an internally timed write cycle or not. this operation is initiated by the stop conditi on after inputting write data. this requires the 8-bit device address word with the 8 th bit = 0 (write) following the start condition during an internally timed write cycle. if the eeprom is busy with the internal wr ite cycle, no acknowledge will be returned. if the eeprom has terminated the internal wr ite cycle, it responds with an acknowledge. the terminated write cycle of the eeprom can be known by this operation. access from master device during write start no ack sda start no ack during write start a c k no write r/w r/w r/w 0 1 0 s1 1 w s2 s0 0 1 0 s1 1w s2 s0 0 1 0 s1 1w s2 s0
le2464c www.onsemi.com 11 7) eeprom read operation 7)-1. current address read the device has an internal address counter. it maintains that last address during the last read or write operation, with incremented by one. the current address read accesses the address kept by the internal address counter. after receiving a start conditi on and the device address word with the 8 th bit = 1 (read), the eeprom outputs the 8-bit current address data from following ac knowledgement 0. if the eeprom receives acknowledgement 1 and a following stop cond ition, the eeprom stops the read operation and is returned to a standby mode. in case the eeprom has accessed the last address of the last page at previous read operation, t he current address will roll over and return s to zero address. in case eeprom has accessed the last address of the last page at previous write operat ion, the current address roll over within page addressing and returns to the first address in the same page. the current address is valid while power is on. after power on, the current address will be reset (all 0). note: after the page write operation, the current addre ss is the specified memory address in the last page write, if the write data is more than 32-bytes. 7)-2. random read the random read requires a dummy write to set read address. the eeprom receives a start condition and the device address word with the 8 th bit = 0 (write), the memo ry address. the eeprom outputs acknowledgement 0 after receiving memory address t hen enters a current address read with receiving a start condition. the eeprom output s the read data of the address whic h was defined in the dummy write operation. after receiving no ac knowledgement and a following st op condition, the eeprom stops the random read operation and returns to a standby mode. access from master device device address ack no ack sto p data (n+1) r/w s d a 0 1 0 s1 1 r start s2 s0 d7 d6 d5 d4 d3 d2 d1 d0 access from master device a c k dummy write device address r/w word address(n) a c k a c k a15 ~ a13: don?t care data(n) ack device address ack no ack stop current read r/w start sda 0 1 0 s1 1 w s2 s0 a 11 a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 s1 1r start s2 s0 d7 d6 ~ d1 d0 a 12 a 14 a 13 a 15
le2464c www.onsemi.com 12 7)-3. sequential read the sequential read operation is initiated by eit her a current address read or random read. if the eeprom receives acknowledgement 0 after 8-bit read data, the re ad address is incr emented and the next 8-bit read data outputs. the current address will roll over and returns address zero if it reaches the last address of the last page. the sequential read ca n be continued after roll over. the sequential read is terminated if the eeprom receives no ac knowledgement and a following stop condition. access from master device d7 d6 ~ d1 d0 data(n) s d a device address 0 1 0 1 s0 r start ack no ack sto p data(n+1) data(n+2) data(n+x) r/w s1 s2 d7 d6 ~ d1 d0 a c k d7 d6 ~ d1 d0 a c k d7 d6 ~ d1 d0 ack
le2464c www.onsemi.com 13 master device eeprom sda c bus r pu i l i l application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, t he sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack out put and read data to be output from the eeprom during the dummy clock period, forcibly enterin g h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin mu st be connected to a pull-up resistor (with a resistance from several k ? to several tens of k ? ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ? i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum value the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time tr and fall time tf must be set. r pu maximum value = (v cc ? v ih ) / i l example : when v cc = 3.0 v and i l = 2 ? a r pu maximum value = (3.0 v ? 3.0 v ? 0.8) / 2 ? a = 300 k ? r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of eeprom must be set. r pu minimum value = (v cc ? v ol ) / i ol example : when v cc = 3.0 v, v ol = 0.4 v and i ol = 1 ma r pu minimum value = (3.0 v ? 0.4) / 1 ma = 2.6 k ? recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load ca pacitance is 50 pf and the sda output data strobe time is 500 ns, r pu will be about r pu = 500 ns/50 pf = 10 k ? . start condition start condition scl sda 1 2 8 9 dummy clock x 9
le2464c www.onsemi.com 14 3) precautions when turning on the power this product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. symbol parameter ratings unit min typ max t rise power rise time ? ? 100 ms t off power off time 10 ? ? ms v bot power bottom voltage ? ? 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instructi on 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. b. if it is not possible to satis fy the instruction 2 in note above after the power has stabilized, so ftware reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) noise filter for the scl and sda pins this product contains a filter circuit for eliminati ng noise at the scl and sda pins. pulses of 100 ns or less are not recognized because of this function. 5) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring ci rcuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3 v and below. v cc 0v toff trise vbot v cc scl sda tlow tdh tsu.dat v cc scl sda tsu.dat
le2464c www.onsemi.com 15 6) notes on write protect operation this product prohibits all memory array writing when the wp pin is high. to ensure full write protection, the wp is set high for all periods from the start cond ition to the stop condition, and the conditions below must be satisfied. symbol parameter ratings unit min typ max t su.wp wp setup time 600 ? ? ns t hd.wp wp hold time 600 ? ? ns 7) slave address setting this product does not have slave address pin of s0 and s1, but the in formation for the slave addresses, s0 and s1, are held internally. the slave addresses of th is product are set to s0=0, and s1=0 when it is shipped. during device addressing, execute this slave address code after the device code. stop condition start condition scl sda t su .wp t hd.wp wp
le2464c www.onsemi.com 16 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. marking information le2464cxa wlp6(1.20x0.80) ordering information device package shipping (qty / packing) LE2464CXATBG wlcsp6, 0.80x1.20 (pb-free / halogen free) 5000 / tape &reel part id : 66c lot number : 3digits 6 6 c lot

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